CppCon talk illustrating how cache hierarchies, branch prediction, alignment, and SIMD influence C++ performance and providing guidelines for writing hardware-conscious, high-speed code.

Practical C++ demonstration of how cache locality and branch prediction affect real-world runtime, showcasing code patterns and optimizations to exploit modern CPU behaviour for faster programs.

Long-form industry analysis show covering semiconductor manufacturing roadmaps, AMD’s 2 nm “Venice” chiplets, yield calculations, HBM4, CHIPS Act developments, and organizational changes at Intel and Nvidia—providing practitioners with deep context on cutting-edge processor and foundry hardware.

Focuses on techniques for high-performance C++ code, aligning with software optimization and best practices.

Technical overview of memristor technology and its role in power-efficient analog in-memory computing for AI accelerators.

Keynote analyzes the limits of Moore’s Law scaling and advocates mixed-signal and ADC-centric approaches for power-efficient RF/digital design.